Modern computer systems are often characterized by a plurality of functionally different types of circuit cards, or agents, which are interconnected by means of a system bus. In order to facilitate the design of such circuit cards and the implementation of software routines necessary to utilize these cards such computer buses are typically standardized. One such bus is a 32-bit high performance synchronous bus known as the P1296, which is also commonly known as Multibus II.
Such a bus typically comprises a plurality of predefined signal lines which are utilized for the transfer of memory addresses and data between two or more circuit boards which are interconnected to the bus. Other signal lines are defined for regulating the transfer of data over the bus, for interrupt events, and for error conditions. Also, one or more clocks are provided by the bus for synchronizing the flow of data between agents. Typically, such a bus will have interconnected thereto at least one circuit card having a data processor contained thereon, such as a microprocessor device. Other circuit cards may comprise input/output (I/O) circuitry for interfacing to external devices such as mass storage devices, CRTs and printers. Other cards interconnected to the bus may be high capacity memory cards which comprise a plurality of read/write memories such as dynamic random access memories (DRAM) which are operable for the storage and retrieval of data. Additionally, a circuit card such as a card adapted for control of a mass storage device may also have a relatively large amount of DRAM for local buffering of data going to and coming from the mass storage device and may also have a local microprocessor device for controlling the mass storage device.
A problem arises when it is desired to transfer relatively large blocks of data between circuit cards on such a bus. Inasmuch as the bus may be considered to be a shared resource which is common to all of the circuit cards which are interconnected to the bus, it is desirable that such data transfers occur in a rapid manner to avoid a reduction in the bandwidth of the bus.
In order to achieve an increased bus bandwidth it has been known to provide a first in/first out (FIFO) buffer upon both a requesting agent and a replying agent. For example, the requesting agent may notify the replying agent that it desires a block of data to be read from a local memory on the replying agent and thereafter transmitted to the requesting agent over the bus. In response thereto the replying agent accesses the desired memory locations and loads the data contained therein into the replying agent's FIFO, the data thereafter being transmitted from the FIFO across the bus to a FIFO on the requesting agent from where the requesting agent may extract and store the data in a local memory. As can be appreciated, the use of such FIFO buffers may result in the system incurring additional costs and complexity. Furthermore, the storage capacity of available FIFO buffers may be insufficient to transfer a desired block size of data, resulting in the requirement that the FIFO be fully loaded two or more times with data.
In other systems it has been known to utilize memory interleaving in order to increase the data transfer speed of the bus. Memory interleaving however may also result in an increased system cost. Also, memory interleaving may increase the speed of only certain types of data transfers.
The problem of achieving or maintaining a high bus bandwidth is also related to a requirement that the memory devices, if they are DRAM devices, be periodically refreshed. This refresh requirement may result in the need to interrupt a block data transfer in order to accomplish the refresh. Also, if a local processor is included on the agent, the local processor may also require access to the memory, thereby also interfering with the transfer of data between agents.